Bit Test Instruction 位检测指令
instruction used bit 指令使用位
bit-parallel logical instruction 位平行逻辑指令
Bit Manipulation Instruction 位操作类指令
Bit Scan Instruction 位扫描指令
The core is based on Harvard architecture with 16-bit instruction length and 8-bit data length. The performance of MCU has been improved greatly by introducing single-clock-cycle instructions, setting multiple high-speed working registers and replacing micro-program with direct logic block etc.
该MCU核采用哈佛结构、16位指令字长和8位数据字长，通过设计单周期指令、在内部设置多个快速寄存器及采用硬布线逻辑代替微程序控制的方法，加快了微处理器的速度，提高了指令的执行效率。
参考来源 - 高速八位RISC微控制器内核设计·2,447,543篇论文数据，部分数据来源于NoteExpress
An 8-bit instruction register can only specify 256 different operations and variations on operations.
一个八位的指令寄存器也只能确定256种不同的操作以及对于这些操作的修改。
An attempt was made to execute a floating point instruction when the floating point available bit in the MSR (machine status register) was disabled.
如果在MSR(机器状态寄存器)中可用的浮点位被禁用，将尝试执行一个浮点指令。
Vega processors included a custom read barrier instruction that included bit field checking in reference metadata as well as special virtual memory protection for GC-compacted pages.
Vega处理器包含了一个客户化的读屏障指令，它具有字段检查元数据和针对GC压缩页面的特殊的虚拟内存保护。
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